The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a technology field for providing a chip prevention member with a higher Young's modulus than a transparent resin layer in a dicing portion and preventing chipping of a semiconductor layer caused in dicing.
Japanese Unexamined Patent Application Publication No. 2008-66679 is an example of the related art.
In recent years, PKGs (packaging) of solid-state imaging elements (image sensors) have been mass-produced in a form called a chip size PKG (hereinafter referred to as a CSP). Such a CSP is different from a cavity PKG of the related art formed of ceramics or a mold resin. For example, as a cavity configuration in which a gap between adjacent chips is spaced by a resin wall on a wafer is formed, a protective layer (for example, transparent glass) and a Si (silicon) wafer of a sensor unit are bonded, a through silicon via (hereinafter referred to as a TSV) is formed, rewiring is performed on an opposite surface to an imaging surface, solder balls are provided, and finally dicing is performed for fragmentation.
FIG. 12A is a diagram illustrating an example of the configuration of a solid-state imaging element (semiconductor device) of a CSP that has the above-mentioned cavity configuration. In the CSP having the cavity configuration, as illustrated in FIG. 12A, a semiconductor layer 100 and a protective layer 102 are bonded by resin walls 103 formed as adhesives. In this case, an inner space 104 partitioned by the semiconductor layer 100, the protective layer 102, and the resin walls 103 is filled with air. As illustrated in the drawing, a plurality of solder balls 101 are formed on a rear surface side of an imaging surface of the semiconductor layer 100.
In the CSP, Deep-RIE or an insulation film (SiO2) is formed through a TSV forming process. However, in order to form the film for excellent productivity, it is necessary to reduce an aspect ratio of a via diameter to the thickness of Si used to form the semiconductor layer 100. Therefore, Si is thinned to a thickness of, for example, about 50 μm to about 100 μm through a back grinding (hereinafter referred to as a BGR) process.
However, since the inner space 104 filled with air is formed in the CSP having the cavity configuration as illustrated in FIG. 12A, a portion that supports Si (semiconductor layer 100) having the above-described thickness of about 50 μm to about 100 μm is very small. Therefore, in particular, in an image sensor with a large size, there is a problem that the semiconductor layer 100 may be bent in a BGR process or may be considerably bent due to stress occurring when the CSP is mounted on a substrate after the BGR process. FIG. 12B is a diagram illustrating an image of bending (warping) of the semiconductor layer 100 in this case.
When the size of an image sensor is a small, an aspect ratio of the thickness to the width of Si is small. Therefore, mechanical rigidity of Si is relatively high and considerable warping rarely occurs. However, when an image sensor has a large size, the aspect ratio of the thickness to the width of Si is large. Therefore, as the mechanical rigidity of Si is weakened, considerable warping easily occurs.
The fact that the semiconductor layer 100 is warped means that the imaging surface is curved. Accordingly, there is a problem that optical accuracy deteriorates due to the curving of an imaging surface. Specifically, when the above-described warping occurs, an optically focused position of a lens is deviated at the center and periphery of a sensor. Therefore, when focusing is achieved at the center, there is a problem that blur occurs at the periphery.
In order to resolve the problems caused due to the CSP having the cavity configuration, a CSP having a cavity-less configuration illustrated in FIG. 13A has been suggested. In the CSP having the cavity-less configuration, as illustrated in FIG. 13A, a gap between the semiconductor layer 100 and the protective layer 102 formed of glass is filled with a transparent adhesive resin and is formed as a transparent resin layer 105. In other words, with regard to the foregoing CSP having the cavity configuration illustrated in FIG. 12A, the inner space 104 is filled not with air but with a transparent resin.
In such a cavity-less configuration, not only the mechanical rigidity of the Si (semiconductor layer 100) single body but also the rigidity of the protective layer 102 formed of relatively thick glass of, for example, about 300 μm to about 800 μm are added in the warping, as illustrated in FIG. 12B. Therefore, since the mechanical rigidity can be increased, it is possible to efficiently prevent the warping from occurring.
However, at a wafer level, the adhesive resin forming the transparent resin layer 105 is bonded to the glass (protective layer 102) on the entire wafer surface in order to realize the above-described cavity-less CSP configuration. Therefore, a film stress should be caused to be as small as possible in the transparent resin forming the transparent resin layer 105. Otherwise, the warping may occur when the Si and the glass are bonded. Here, the fact that the stress is caused to be small means that a modulus generally also decreases (softens). Accordingly, in order to realize the cavity-less configuration, as illustrated in FIG. 13A while preventing the above-described warping from occurring, it is necessary to decrease the modulus of the transparent resin forming the transparent resin layer 105 (lower the Young's modulus).